Approximately 3 Watts , achieved through a high-efficiency 28nm FD-SOI (Fully Depleted Silicon On Insulator) manufacturing process.
Up to 2.5 Tera Operations Per Second (TOPS) .
Detailed hardware integration data for the EyeQ4-Mid and EyeQ4-High includes: Flip-Chip FBGA with 784 pins . Dimensions: 22.5 mm x 22.5 mm x 1.7 mm. eyeq4 datasheet
2 Cores using a CGRA dataflow machine architecture for dense computer vision algorithms. EyeQ4 Family Variants
Efficiently fuses data from optical sensors with radar and scanning-beam lasers. Physical and Electrical Characteristics Approximately 3 Watts , achieved through a high-efficiency
A subset version tailored for mid-range ADAS. It integrates fewer cores (e.g., three MIPS cores and four VMP cores) and is typically used in single-camera or trifocal configurations.
Quad-core processors with multi-threading (up to 4 threads per core). VMP Vector Microcode Processor Dimensions: 22
The is a high-performance vision-based System-on-Chip (SoC) designed specifically for Advanced Driver Assistance Systems (ADAS) and autonomous driving . Leveraging a heterogeneous multi-core architecture, it delivers significant leaps in computational efficiency compared to its predecessors.
The EyeQ4 datasheet highlights several next-generation ADAS capabilities: